Cite this Article
Han Ru, Zhang Hai-Chao, Wang Dang-Hui, Li Cui. Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer. Chinese Physics B, 2019, 28(1): 018505  
Permissions
Optimization of ambipolar current and analog/RF performance for T-shaped tunnel field-effect transistor with gate dielectric spacer
Han Ru †, Zhang Hai-Chao, Wang Dang-Hui, Li Cui
School of Computer Science and Engineering, Northwestern Polytechnical University, Xi’an 710072, China

 

† Corresponding author. E-mail: hanru@nwpu.edu.cn

Abstract

A new T-shaped tunnel field-effect transistor (TTFET) with gate dielectric spacer (GDS) structure is proposed in this paper. To further studied the effects of GDS structure on the TTFET, detailed device characteristics such as current-voltage relationships, energy band diagrams, band-to-band tunneling (BTBT) rate and the magnitude of the electric field are investigated by using TCAD simulation. It is found that compared with conventional TTFET and TTFET with gate-drain overlap (GDO) structure, GDS-TTFET not only has the minimum ambipolar current but also can suppress the ambipolar current under a more extensive bias range. Furthermore, the analog/RF performances of GDS-TTFET are also investigated in terms of transconductance, gate-source capacitance, gate-drain capacitance, cutoff frequency, and gain bandwidth production. By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure can effectively reduce parasitic capacitances between the gate and the source/drain, which leads to better performance in term of cutoff frequency and gain bandwidth production. Finally, the thickness of the gate dielectric spacer is optimized for better ambipolar current suppression and improved analog/RF performance.

PACS: 85.30.De;85.30.Tv;85.30.Mn
Keyword:tunneling field effect transistor;T-shaped tunnel field-effect transistor;gate dielectric spacer;ambipolar current;analog/RF performance
1. Introduction

As MOSFETʼs sizes continually scaling, the characteristics of MOSFET are affected by various short-channel effects (SCEs), such as drain-induced barrier lowering, surface scattering, and so on.[1–3] In addition, as device sizes continue to shrink, the effects of subthreshold leakage currents on device power consumption are becoming more and more severe.[4–6] However, for MOSFET, the carrier injection in source-channel junction is governed by thermionic emission over the build-in potential barrier and hence the inverse subthreshold slope is limited to 60 mV/decade at room temperature.[7,8] Therefore, tunnel field-effect transistor (TFET) has been actively investigated as one of the most promising candidates for future ultra-low power applications. Due to its band-to-band tunneling (BTBT) based carrier injection mechanism, TFET can overcome the 60 mV/dec subthreshold swing limitation of conventional MOSFET.[9–15] However, low on-current and sizeable ambipolar current are major shortcomings of traditional silicon-based TFET, which limit the use of TFET in low-power and high-frequency applications.[16–21] To improve the drive current while reducing the footprint of TFET, various L-shaped architectures based on gate-source overlap structure and vertical channel have been proposed.[22–32] However, it has been pointed out that conventional L-TFET suffers from severe ambipolar behavior, which needs further optimizations.[32,33]

Recently, a T-shaped TFET (TTFET) with gate-drain overlap (GDO) structure has been proposed to improve the drive current and suppress the ambipolar current simultaneously.[34] However, it is found that this T-shaped TFET with GDO structure (GDO-TTFET) can only suppress ambipolar current when Vds is low. Besides, the GDO structure also increases the gate-drain capacitance, resulting in poor RF/analog performance.

To suppress the ambipolar current under a more extensive bias range while improving the RF/analog performance, a new T-shaped TFET with gate dielectric spacer (GDS) structure is proposed in this paper. TCAD simulation results show that our proposed T-shaped TFET with GDS (GDS-TTFET) not only suppress ambipolar current over a broader bias range but also improves analog/RF performance compared with GDO-TTFET. To implement the proposed GDS structure, just a layer of low-κ dielectric needs to insert between the high-κ dielectric and gate electrode material. Additionally, the process of the GDS-TTFET is compatible with the self-aligned process used in Ref. [33], which makes the process of GDS-TTFET much simpler than that of GDO-TTFET.

2. Device structure and simulation method

The proposed T-shaped TFET with gate dielectric spacer (GDS-TTFET) is shown in Fig. 1(a). The device contains two vertical gate-overlapped channels and two lightly doped p-type tunneling regions located between the source and the gate dielectric layer. Below the gate electrode, a low-κ dielectric spacer is inserted between the gate electrode and the high-κ gate dielectric. Based on the process steps of LTFET demonstrated in Ref. [33], T-shaped TFET (TTFET) with symmetrical vertical double gate structure can be easily fabricated. Therefore, based on conventional TTFET processes, the structure proposed in this paper can be achieved only by adding a layer of gate dielectric spacer.

Fig. 1. Cross-sectional view of (a) proposed GDS-TTFET, (b) conventional TTFET, and (c) GDO-TTFET proposed in Ref. [34].

The detailed device parameters are listed below: height of the gate HG = 50 nm, height of the source HS = 30 nm, height of the drain HD = 10 nm, width of the gate WG = 10 nm, width of the source WS = 20 nm, width of tunneling region between the source and the gate dielectric layer Wtun = 3 nm, thickness of the high-κ gate dielectric TOX = 2 nm, the default height of the inserted low-κ gate dielectric spacer Hspacer = 4 nm), gate work function Φ = 4.2 eV, p+ type source doping NS = 1020 cm−3, p− type channel doping NSub = 1017 cm−3, and n+ type drain doping ND = 1020 cm−3. For comparison, conventional TTFET and GDO-TTFET proposed in Ref. [34] are also demonstrated in Figs. 1(b) and 1(c), respectively.

In this paper, the three devices mentioned above are all silicon-based and investigated by using Sentaurus TCAD with a dynamic nonlocal tunneling model. With this dynamic nonlocal tunneling approach, tunneling paths are dynamically determined according to the variation of the electric field, so it can model the tunneling process more accurately, especially for non-planner TFET like L-shaped and T-shaped TFET. According to Ref. [37], two calibrated Kaneʼs tunneling model coefficients for silicon are and B = 9.9 × 106 V/cm. In addition to using the BTBT model, the OldSlotboom band-gap narrowing model and Shockley–Read–Hall recombination model are also used in the TCAD simulations. For simplicity, an idealized device structure with abrupt source/drain-channel junctions has been considered, and the defect-related traps and charges are ignored in this paper.

3. Simulation results and discussion
3.1. Performance comparison between conventional TTFET, GDO-TTFET, and GDS-TTFET

The Ids–Vgs for conventional TTFET, GDO-TTFET, and GDS-TTFET at Vds = 1.5 V is shown in Fig. 2. It is clear that when Vgs is negatively biased from −2.0 V to 0 V, the GDS-TTFET has the lowest ambipolar current. Especially, when Vgs = −1.0 V, the bipolar current of the GDS-TTFET is reduced to the order of , which is 4 orders of magnitude smaller than that of conventional TTFET and 5 orders of magnitude lower than that of GDO-TTFET. It is also noticed that since the source structure of conventional TTFET, GDO-TTFET, and GDS-TTFET are identical, the Ids–Vgs of those three devices are the same when Vgs is positively biased from 0 V to 2.0 V.

Fig. 2. Ids–Vgs for conventional TTFET, GDO-TTFET, and GDS-TTFET with Vds = 1.5 V.

To further explain why the GDS structure can effectively suppress the ambipolar current, energy band profiles of conventional TTFET, GDO-TTFET, and GDS-TTFET are plotted in Fig. 3. It can be seen that when Vds = 1.5 V and Vgs = −2.0 V, the conduction band of the drain is far below the valence band of the channel, which produces a wide tunneling window for holes from the conduction band of the drain to the valence band of the channel when gate voltage is negatively biased. As the tunneling windows appears, the band to band tunneling (BTBT) probability is mainly determined by the width of the tunneling barrier, which is defined as the closest distance between the conduction band and the valence band when tunneling window is open. By inserting the low-κ gate dielectric spacer between the gate electrode and the gate dielectric, the GDS structure effectively reduces the influence of the gate bias on the lateral channel potential when the gate voltage is reversely biased at Vgs = −2.0 V, leading to a slow variation of energy band profile. It can be seen from Fig. 3 that GDS-TTFET has the widest tunneling distance, which means the smallest tunneling probability, and thus the lowest ambipolar current when the gate voltage is negatively biased.

Fig. 3. Energy band diagram alone the channel at Vds = 1.5 V and Vgs = −2.0 V for conventional TTFET, GDO-TTFET, and GDS-TTFET.

It also should be noticed that although GDO-TTFET has a wider tunneling width than conventional TTFET, it has larger ambipolar current than conventional TTFET. This because that by using gate-drain overlap (GDO) structure, BTBT current of GDO-TTFET is dominated by the tunneling component perpendicular to the channel, which also referred to as “line tunneling”.[11]

Figure 4 shows the energy band diagram perpendicular to the channel for conventional TTFET, GDO-TTFET, and GDS-TTFET. It can be seen that the energy band diagram of the GDO-TTFET has the most significant band bending curvature at the channel surface, resulting in a small tunneling distance between the valence band and the conduction band, thereby causing substantial “line tunneling” BTBT current. However, for GDS-TTFET, the band-bending curvature perpendicular to the channel direction is so small that there are no tunneling windows and no “line tunneling” occurs.

Fig. 4. Energy band diagram perpendicular to the channel at Vds = 1.5 V and Vgs = −2.0 V for conventional TTFET, GDO-TTFET, and GDS-TTFET.

For better explanation, 2D contour plots of the BTBT generation GBTBT for conventional TTFET, GDO-TTFET, and GDS-TTFET at Vds = 1.5 V and Vgs = −2.0 V are shown in Fig. 5. According to Fig. 5, the GBTBT peak value of the GDS-TTFET is on the order of 1025, which is 6 orders of magnitude smaller than that of the conventional TTFET and GDO-TTFET. Since higher GBTBT and larger BTBT distribution area will result in greater tunneling current, the GDS-TTFET has the lowest ambipolar current. In addition, although the GBTBT peak value of conventional TTFET and the GDO-TTFET is of the same order of magnitude, since the tunneling area of the GDO-TTFET is much larger than that of the conventional TTFET, the GDO-TTFET has the largest ambipolar tunneling current when gate voltage is biased at Vgs = −2.0 V.

Fig. 5. 2D contour plots of the BTBT generation GBTBT for conventional TTFET (a), GDO-TTFET (b), and GDS-TTFET (c) with Vds = 1.5 V and Vgs = −2.0 V.

The electric field variation along the channel surface from channel to drain for conventional TTFET, GDO-TTFET, and GDS-TTFET are shown in Fig. 6. As can be seen from Fig. 6, for conventional TTFET and GDS-TTFET, there is a spike of electric field variation at the interface between channel region and drain region. According to Kaneʼs theory, when band-to-band tunneling occurs, the tunneling probability exponentially depends on the local electric field strength. It can be seen that the electric field strength of the GDS-TTFET near the channel/drain interface is much smaller than that of the conventional TTFET, which means that GDS-TTFET has lower ambipolar current than conventional TTFET. Due to the gate-drain overlap structure used in GDO-TTFET, the electric field variation of the GDO-TTFET is different from that of conventional TTFET and GDS-TTFET. In the whole gate-drain overlap region, the electric field strength of the GDO-TTFET remains constant at around 1.0 × 107 V/cm, which lead to significant “line tunneling” current.

Fig. 6. Electric field variation alone the channel surface from channel to drain for conventional TTFET, GDO-TTFET, and GDS-TTFET with Vds = 1.5 V and Vgs = −2.0 V.

Further, the spike of the electric field variation present at the surface of drain/channel junction is the primary cause of the hot carrier effects, which will lead to threshold voltage roll-off and poor device reliability.[35] It is shown in Fig. 6 that the GDS structure can help to reduce the surface electric field near the drain/channel junction. For GDS-TTFET, the electric field is about 3 times smaller than conventional TTFET. Therefore, compared with conventional TTFET, GDS-TTFET has better suppression of hot carrier effects, hence smaller threshold voltage roll-off and better device reliability.

When Vds is small, GDS-TTFET still has the advantage over conventional TTFET and GDO-TTFET. As shown in Fig. 7, when Vgs is biased at specific voltage range, the ambipolar is equal to the OFF-state current of TTFET, which means TTFET is turned off. It can be seen that the GDS-TTFET has the broadest OFF-state range compared with others ( for TTFET, for GDO-TTFET, and for GDS-TTFET). This unique feature of GDS-TTFET makes it have a better application prospect in integrated circuits.

Fig. 7. Transfer characteristics for conventional TTFET, GDO-TTFET, and GDS-TTFET with Vds = 0.5 V.
3.2. Parasitic capacitance and analog/RF performance

By inserting a low-κ spacer layer between the gate electrode and the gate dielectric, the GDS structure not only effectively suppress the bipolar current, but also reduce parasitic capacitances between the gate and the source/drain, which are vital parameters for analog/RF performance of TTFET. Figure 8 shows the gate-source and the gate-drain parasitic capacitance versus gate voltage for conventional TTFET, GDO-TTFET, and GDS-TTFET. For simplicity, Vds = 1.0 V, AC simulation frequency is set to 1 MHz.

Fig. 8. Gate-source and gate-drain parasitic capacitance versus gate voltage for conventional TTFET, GDO-TTFET, and GDS-TTFET with Vds = 1.0 V.

It can be seen that compared to conventional TTFET and GDO-TTFET, GDS-TTFET not only has smaller gate-source capacitance but also has smaller gate-drain capacitance, which has a significant impact on cutoff frequency fT and gain bandwidth production (GBP).

In addition, it is also found that the gate-source capacitance Cgs and the gate-drain capacitance Cgd have opposite trends with the gate voltage Vgs. For TFETs, the source and drain regions have different types of doping. In this paper, the source region is heavily doped with P-type dopant and the drain region is heavily doped with N-type. So the source region is hole-rich region, while drain region is electron-rich region. When the Vgs is biased in the negative range, the inversion layer in the channel is of holes. Thus the gate-source capacitance Cgs is larger than the gate-drain capacitance Cgd, and the gate-source capacitance Cgs becomes larger as the gate voltage is biased more negative. On the contrary, when the Vgs is biased in the positive range, the gate-source capacitance Cgs becomes small, the gate-drain capacitance Cgd is dominant. Since the analog/RF performance of TTFET is mainly analyzed under the forward operating mode ( ), the gate-drain capacitance has a more significant influence on analog/RF performance than the gate-source capacitance.

Another parameter closely related to analog/RF performance is the transconductance gm of the TTFET. The gm of the TTFET device is primarily determined by its forward conduction characteristics, which is mainly dependent on the gate-source structure of the device. Figure 9 shows the transfer characteristics for conventional TTFET, GDO-TTFET, and GDS-TTFET with Vds = 1.0 V. It can be seen that since those three TTFET devices have identical gate-source structures, their forward conduction characteristics are the same Ids−Vgs relationship or logIds–Vgs relationship. In other words, when Vgs is biased within the positive voltage range, those three TTFET devices have the same transconductance.

Fig. 9. Transfer characteristics for conventional TTFET, GDO-TTFET, and GDS-TTFET with Vds = 1.0 V.

Based on transconductance and parasitic capacitance, two other essential figures-of-merits for analog/RF applications are available: cutoff frequency fT and gain bandwidth product (GBP). The cutoff frequency depends on the ratio of transconductance to the total capacitance and can be defined as

where gm is the transconductance, Cgs and Cgd are gate to source and gate to drain intrinsic parasitic capacitances.[36]

Figure 10 shows the comparisons of fT as a function of gate voltage for conventional TTFET, GDO-TTFET, and GDS-TTFET. For all these three TTFET devices, it can be seen that cutoff frequency fT increases with gate voltage increasing and reaches the maximum value when the gate voltage is biased at a specific value, and then the fT decreases as the gate voltage continues to increase. Moreover, it can be seen that due to the reduced parasitic gate-drain capacitances, GDS-TTFET attains the highest values of fT as compared with conventional TTFET and GDO-TTFET.

Fig. 10. Cut-off frequency for conventional TTFET, GDO-TTFET, and GDS-TTFET at Vds = 1.0 V.

Due to its gate-drain overlap structure, the GDO-TTFE has the largest parasitic gate-drain capacitance among these three TTFET devices, so with the same transconductance, the fT of the GDO-TTFET is always the smallest when Vgs is biased from 0 V to 2.0 V.

The same variation tendencies of gain bandwidth product (GBP) can be found in Fig. 11, while the GBP is defined as

where gm is the transconductance and Cgd is the gate to drain intrinsic parasitic capacitances.[26] Among these three TTFET devices, the GDS-TTFET has the smallest parasitic gate-drain capacitance Cgd, so when the transconductance of the three devices is the same, the GDS-TTFET has the largest GPB.

Fig. 11. Gain bandwidth production for conventional TTFET, GDO-TTFET, and GDS-TTFET at Vds = 1.0 V.

It also should be noticed that both maximum fT and maximum GBP of this three TTFET are less than 1 GHz, because silicon-based TTFET still has low on-current ION due to the siliconʼs relatively large energy band gap and sizeable effective tunneling mass.[12] Low ION means small transconductance, which put a limitation on maximum fT and GBP. Therefore, in the future work, III–V materials and heterojunction structures can be introduced into the TTFET to boost the on-state current and further improve the analog/RF characteristics.

3.3. Parameter optimization for GDS-TTFET

For GDS-TTFET devices, the thickness of the low-κ dielectric layer inserted between the gate electrode and the gate dielectric is represented by parameter Hspacer, which has an enormous influence on the GDS-TTFETʼs performances in terms of bipolar current suppression capability and analog/RF characteristics.

Figure 12 shows the transfer characteristics of the GDS-TFET with different Hspacer. It can be seen that when the gate voltage is negatively biased, the larger the Hspacer is, the weaker the control ability of the gate electrode to the channel is, and the smaller the ambipolar tunneling current generated. However, if the Hspacer is larger than 4 nm, the gate control ability to the tunneling region (between the gate and the source) will also deteriorate as Hspacer increases, resulting in a decrease in the ION.

Fig. 12. Transfer characteristics for GDS-TTFET with different Hspacer at Vds = 1.0 V.

To further investigate the impact of Hspacer on the GDS-TTFETʼs on-current ION, figure 13 shows the effect of Hspacer on the transconductance of GDS-TTFET when Vgs is biased from 1.0 V to 2.0 V. It can be seen that when Hspacer is less than 4 nm, the GDS structure has almost no influence on the transconductance of the GDS-TTFET. However, when Hspacer is larger than 6 nm, the transconductance of the GDS-TFET is significantly reduced. Also, as shown in Fig. 14, larger Hspacer means smaller gate-source and gate-drain parasitic capacitances, which is beneficial to improve the analog/RF characteristics of the GDS-TTFET.

Fig. 13. Transconductance of the GDS-TTFET with different Hspacer at Vds = 1.0 V when Vgs is biased from 1.0 V to 2.0 V.
Fig. 14. Gate-source and gate-drain parasitic capacitance versus gate voltage for GDS-TTFET with different Hspacer at Vds = 1.0 V.

In order to comprehensively analyze the influence of Hspacer on the analog/RF performance of the GDS-TTFET, the effects of Hspacer on the cutoff-frequency fT and the gain bandwidth product (GBP) of the GDS-TTFET are shown in Figs. 15 and 16, respectively.

Fig. 15. Cut-off frequency for the GDS-TTFET with different Hspacer at Vds = 1.0 V.
Fig. 16. Gain bandwidth product (GBP) for the GDS-TTFET with different Hspacer at Vds = 1.0 V.

It can be seen from Fig. 15 that the GDS structure has a significant improvement on the cutoff frequency characteristics of the GDS-TTFET. Especially, when Hspacer is equal to 4 nm, the cutoff frequency fT of the GDS-TTFET can obtain a higher peak value around 7 × 108 Hz, and this peak value can be maintained over a wider Vgs bias range. However, when Hspacer is increased to 6 nm, the cutoff frequency characteristic of the GDS-TTFET starts to degrade, both the cutoff frequency peak value and the Vgs bias range with high cutoff frequency will decrease.

Same variation tendencies of gain bandwidth product (GBP) can be found in Fig. 16, when Hspacer is equal to 4 nm, the peak value of the GBP is the highest, but when Hspacer is further increased, the peak value of the GPB will decrease gradually.

Therefore, it is necessary to optimize the Hspacer of the GDS-TTFET. By selecting the appropriate Hspacer, the GDS-TTFET can effectively suppress the bipolar current and reduce the gate-drain parasitic capacitance while keeping the ION unaffected, thus obtaining the best analog/RF performance.

4. Conclusion

To better suppress the ambipolar current under a broader bias range while reducing the gate-drain and gate-source parasitic capacitances, a new T-shaped TFET (TTFET) with gate dielectric spacer (GDS) structure is proposed in this paper. Ids–Vgs characteristics analysis shows that by inserting a low-κ gate dielectric spacer between the gate electrode and the gate dielectric, the ambipolar current of the TTFET can be drastically reduced. According to the energy band diagrams both in directions parallel and perpendicular to the channel, GDS-TTFET has the widest tunneling barrier, which results in the smallest BTBT generation and lowest ambipolar tunneling current. Further, analog/RF performance of GDS-TTFET are investigated regarding parasitic capacitance, cutoff frequency and gain bandwidth production. Simulation results show that due to the reduced value of total capacitance, GDD-TTFET has the highest amounts of cutoff frequency and gain bandwidth production as compared with conventional TTFET and GDO-TTFET. Finally, according to our simulations, the thickness of the gate dielectric spacer Hspacer = 4 nm is the best option for ambipolar current suppression and analog/RF performance improvement. The theoretical simulation results of this paper not only provide insights for understanding the physical mechanism of the TTFET, but also have theoretical guiding significance for designing and optimizing TTFET devices in the future.

Reference
[1] Taur Y Buchanan D A Chen W Frank D J Ismail K E Lo S H SaiHalasz G A Viswanathan R G Wann H J C Wind S J Wong H S 1997 Proceedings of the IEEE 85 486
[2] Frank D J Dennard R H Nowak E Solomon P M Taur Y Wong H S P 2001 Proceedings of the IEEE 89 259
[3] Colinge J P 2004 Solid-State Electronics 48 897
[4] Wang P F Hilsenbeck K Nirschl T Oswald M Stepper C Weis M Schmitt-Landsiedel D Hansch W 2004 Solid-State Electronics 48 2281
[5] Frank D J 2002 IBM Journal of Research and Development 46 235
[6] Iwai H 2009 Microelectronic Engineering 86 1520
[7] Zhang Q Zhao W Seabaugh A 2006 IEEE Electron Device Letters 27 297
[8] Choi W Y Park B G Lee J D Liu T J K 2007 IEEE Electron Device Letters 28 743
[9] Boucart K Ionescu A M 2007 IEEE Transactions on Electron Devices 54 1725
[10] Mayer F Royer C L Damlencourt J F Romanjek K Andrieu F Tabone C Previtali B Deleonibus S 2008 IEEE International Electron Devices Meeting 2008 1
[11] Verhulst A S Vandenberghe W G Maex K Groeseneken G 2008 J. Appl. Phys. 104 064514
[12] Seabaugh A C Zhang Q 2010 Proceedings of the IEEE 98 2095
[13] Ionescu A M Riel H 2011 Nature 479 329
[14] Guan Y H Li Z C Luo D X Meng Q Z Zhang Y F 2016 Chin. Phys. B 25 108502
[15] Kang H Y Hu H Y Wang B 2016 Chin. Phys. B 25 118501
[16] Toh E H Wang G H Chan L Samudra G Yeo Y C 2007 Appl. Phys. Lett. 91 243505
[17] Kao K H Verhulst A S Vandenberghe W G Soree B Groeseneken G De Meyer K 2012 IEEE Transactions on Electron Devices 59 292
[18] Vandooren A Leonelli D Rooyackers R Arstila K Groeseneken G Huyghebaert C 2012 Solid-State Electronics 72 82
[19] Raad B Nigam K Sharma D Kondekar P 2016 Electronics Letters 52 770
[20] Jiang Z Zhuang Y Q Li C Wang P Liu Y Q 2016 Chinese Physics B 25 027701
[21] Feng S Zhang Q Yang J Lei M Quhe R 2017 Chin. Phys. B 26 097401
[22] Low K L Zhan C Han G Yang Y Goh K H Guo P Toh E H Yeo Y C 2012 Jpn J. Appl. Phys. 51 02BC04
[23] Kim S W Choi W Y Sun M C Kim H W Park B G 2012 Jpn J. Appl. Phys. 51 06FE09
[24] Kim J H Kim S W Kim H W Park B G 2015 Electronics Letters 51 718
[25] Yang Z 2016 IEEE Electron Device Letters 37 839
[26] Li W Liu H Wang S Chen S 2016 Superlattices and Microstructures 100 1238
[27] Li W Liu H Wang S Chen S Yang Z 2017 Nanoscale Research Letters 12 198
[28] Imenabadi R M Saremi M Vandenberghe W G 2017 IEEE Transactions on Electron Devices 64 4752
[29] Yang Z Zhang Y Yang Y Yu N 2017 Superlattices and Microstructures 111 1226
[30] Zhang W H Li Z C Guan Y H Zhang Y F 2017 Chin. Phys. B 26 018504
[31] Li C Yan Z R Zhuang Y Q Zhao X L Guo J M 2018 Chin. Phys. B 27 078502
[32] Li C Zhao X Zhuang Y Yan Z Guo J Han R 2018 Superlattices and Microstructures 115 154
[33] Kim S W Kim J H Liu T J K Choi W Y Park B G 2016 IEEE Transactions on Electron Devices 63 1774
[34] Dubey P K Kaushik B K 2017 IEEE Transactions on Electron Devices 64 3120
[35] Ding L Gnani E Gerardin S Bagatin M Driussi F Palestri P Selmi L Royer C L Paccagnella A 2015 IEEE Transactions on Device and Materials Reliability 15 236
[36] Ghosh S Koley K Sarkar C K 2015 Microelectronics Reliability 55 326
[37] Kwon D W Kim H W Kim J H Park E Lee J Kim W Kim S Lee J H Park B G 2017 IEEE Transactions on Electron Devices 64 1799